sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns ? battery backup: 2v data retention ? high-performance, low-power cmos double-metal process ? single +5v ( +10%) power supply ? easy memory expansion with ce\ ? all inputs and outputs are ttl compatible options marking ? timing 12ns access -12 15ns access -15 20ns access -20 25ns access -25 35ns access -35 45ns access -45* 55ns access -55* 70ns access -70* ? package(s) ceramic dip (300 mil) c no. 105 ? operating temperature ranges industrial (-40 o c to +85 o c) it military (-55 o c to +125 o c) xt ? 2v data retention/low power l *electrical characteristics identical to those provided for the 35ns access devices. pin assignment (top view) available as military specifications ? smd 5962-86015 ? mil-std-883 general description the austin semiconductor sram family employs high-speed, low-power cmos designs using a four-transistor memory cell. austin semiconductor srams are fabricated using double-layer metal, double-layer polysilicon technology. for flexibility in high-speed memory applications, austin semiconductor offers chip enable (ce\) on all organizations. this enhancement can place the outputs in high-z for additional flexibility in system design. the x1 configuration features separate data input and output. writing to these devices is accomplished when write enable (we\) and ce\ inputs are both low. reading is accomplished when we\ remains high and ce\ goes low. the device offers a reduced power standby mode when disabled. this allows system designs to achieve low standby power requirements. all devices operate from a single +5v power supply and all inputs and outputs are fully ttl compatible. 64k x 1 sram sram memory array for more products and information please visit our web site at www.austinsemiconductor.com 22-pin dip (c) (300 mil) 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 a0 a1 a2 a3 a4 a5 a6 a7 q we\ vss vcc a15 a14 a13 a12 a11 a10 a9 a8 d ce\
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram truth table row decoder 65,536-bit memory array i/o control v cc gnd d we\ a a a a a a a column decoder a a a a a a a a a power down ce\ (lsb) (lsb) q mode ce\ we\ dq power standby h x high-z standby read l h q active write l l high-z active
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 absolute maximum ratings* voltage on any input relative to vss................-2.0v to +7.0v voltage on vcc supply relative to vss............-1.0v to +7.0v voltage applied to q.........................................-1.0v to +7.0v storage temperature...................................-65 o c to +150 o c power dissipation.................................................................1w max junction temperature............................................+175 c lead temperature (soldering 10 seconds)...................+260 o c short circuit output current...........................................50ma *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (-55 o c < t c < 125 o c; v cc = 5v +10%) capacitance description conditions sym min max units notes input high (logic 1) voltage v ih 2.2 vcc+1.0v v 1 input low (logic 0) voltage v il -0.5 0.8 v 1, 2 input leakage current 0v < v in < v cc il i -10 10 a output leakage current outputs disabled 0v < v out < v cc il o -10 10 a output high voltage i oh = -4.0ma v oh 2.4 --- v 1 output low voltage i ol = 8.0ma v ol --- 0.4 v 1 sym -12 -15 -20 -25 -35 units notes i cc 140 125 110 100 90 ma 3 power supply current: standby i sbt1 45 41 36 33 30 ma i sbt2 25 25 25 25 25 ma i sbc2 55555ma power supply current: operating parameter ce\ > (v cc -0.2); v cc = max all other inputs < 0.2v or > (v cc - 0.2v), f = 0 hz ce\ > v ih ; v cc = max f = 1/t rc (min) hz max conditions ce\ < v il ; v cc = max output open ce\ > v ih ; all other inputs < v il or > v ih , v cc = max f = 0 hz description conditions sym max units notes input capacitance c i 6pf 4 output capacitance c o 7pf 4 t a = 25 o c, f = 1mhz vcc = 5v
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 electrical characteristics and recommended ac operating conditions (note 5) (-55 o c < t c < 125 o c; v cc = 5v +10%) min max min max min max min max min max read cycle read cycle time t rc 12 15 20 25 35 ns address access time t aa 12 15 20 25 35 ns chip enable access time t ace 10 13 15 20 25 ns output hold from address change t oh 22222 ns chip enable to output in low-z t lzce 22222 ns7 chip disable to output in high-z t hzce 7 8 10 12 15 ns 6, 7 chip enable to power-up time t pu 00000 ns chip disable to power-down time t pd 12 15 20 25 35 ns write cycle write cycle time t wc 12 15 20 25 35 ns chip enable to end of write t cw 10 12 15 20 25 ns address valid to end of write t aw 10 12 15 20 25 ns address setup time t as 00000 ns address hold from end of write t ah 00000 ns write pulse width t wp 10 12 15 20 25 ns data setup time t ds 7 8 10 12 15 ns data hold time t dh 00000 ns write disable to output in low-z t lzwe 22222 ns7 write enable to output in high-z t hzwe 060708010015ns 6, 7 notes description -12 symbol units -35 -25 -20 -15
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 ac test conditions input pulse levels ...................................... vss to 3.0v input rise and fall times ......................................... 5ns input timing reference levels ................................ 1.5v output reference levels ....................................... 1.5v output load ................................. see figures 1 and 2 notes 1. all voltages referenced to v ss (gnd). 2. -3v for pulse width < 20ns 3. i cc is dependent on output loading and cycle rates. the specified value applies with the outputs unloaded, and f = 1 hz. t rc (min) 4. this parameter is sampled. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. t hzce and t hzwe are specified with cl = 5pf as in fig. 2. transition is measured 500mv typical from steady state voltage, allowing for actual tester rc time constant. 7. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe . 8. we\ is high for read cycle. 9. device is continuously selected. chip enable is held in its active state. 10. address valid prior to, or coincident with, latest occurring chip enable. 11. t rc = read cycle time. 12. chip enable (ce\) and write enable (we\) can initiate and terminate a write cycle. fig. 1 output load equivalent fig. 2 output load equivalent data retention electrical characteristics (l version only) 123 1 2 3 1 2 3 123 1 23 4 1 23 4 1 23 4 1234 dont care undefined low vcc data retention waveform 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 123456789 123456789 123456789 123456789 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 data retention mode v dr > 2v 4.5v 4.5v v dr t cdr t r v ih v il v cc ce\ 5 pf +5v q 255 480 +5v q 255 30pf 480 description sym min max units notes v cc for retention data v dr 2 --- v v cc = 2v i ccdr --- 300 a v cc = 3v i ccdr --- 500 a chip deselect to data retention time t cdr 0 --- ns 4 operation recovery time t r t rc --- ns 4, 11 conditions data retention current ce\ > (v cc - 0.2v) v in > (v cc - 0.2v) or < 0.2v
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 123 1 2 3 123 12345 1 234 5 1 234 5 1 234 5 12345 dont care undefined read cycle no. 1 8, 9 read cycle no. 2 7, 8, 10 q
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 write cycle no. 2 7, 12, 13 (write enabled controlled) 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 dont care undefined write cycle no. 1 12 (chip enabled controlled)
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 mechanical definitions* asi case #105 (package designator c) smd 5962-86015, case outline x note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. d e pin 1 a q l e b b1 s1 l1 s s2 e1 c min max a --- 0.200 b 0.014 0.023 b1 0.030 0.065 c 0.008 0.015 d --- 1.260 e 0.220 0.310 e1 0.290 0.320 e l 0.125 0.200 l1 0.150 --- q 0.015 0.060 s --- 0.080 s1 0.005 --- s2 0.005 --- symbol 0.100 bsc smd specifications
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing -55 o c to +125 o c ** options l = 2v data retention/low power ordering information device number package type speed ns options** process mt5c6401 c -12 l /* mt5c6401 c -15 l /* mt5c6401 c -20 l /* mt5c6401 c -25 l /* mt5c6401 c -35 l /* mt5c6401 c -45 l /* mt5c6401 c -55 l /* mt5c6401 c -70 l /* example: mt5c6401c-45l/883c
sram mt5c6401 austin semiconductor, inc. mt5c6401 rev. 1.0 8/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 asi to dscc part number cross reference* asi package designator c smd 5962-86015 asi p ar t # smd p ar t # mt5c6801c-35/883c 5962-8601501xa mt5c6801c-35l/883c 5962-8601502xa mt5c6801c-45/883c 5962-8601503xa mt5c6801c-45l/883c 5962-8601504xa mt5c6801c-55/883c 5962-8601505xa mt5c6801c-55l/883c 5962-8601506xa * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd.
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